Design Verification Engineer Interview Questions

3,716 design verification engineer interview questions shared by candidates

Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
avatar

ASIC Design Verification Engineer

Interviewed at Apple

4.2
Mar 9, 2021

Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span

Viewing 791 - 800 interview questions

Glassdoor has 3,716 interview questions and reports from Design verification engineer interviews. Prepare for your interview. Get hired. Love your job.