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Design Verification Interview Questions
3,713 design verification interview questions shared by candidates
What is one area you can be better at?
What I know about verilog
Tomasulo project
Simplify the following circuit: One adder takes A and B as input, another adder takes C and D as input. Both adder's output connects to a MUX controlled by signal S, and the output of the MUX goes into a FF
they ask me my preference of work
What is the problem of cache coherency
Second interview question: Given the following assembly commands: MOV Ri <-- Rj/immediate (put register j or immediate value into reg i) INC Ri (++) DEC Ri (--) JNZ Ri (jump not zero) 1. Code an assembly program that calculates x*y where x and y are unsigned integers 2. What values of x and y will cause the program to fail? 3. Modify the program to deal with these values 4. What result will we get if we run the program with values from question 2 and no modification from question 3? 5. Is it possible to answer question 1 without MOV command? Prove it!
Describe memory BIST architecture, march algorithm, MATS test. String parsing questions to process/filter verilog code encased in ifdef/ifndef. How to set up testbench for, and maximize test coverage for scan debug verification. The engineering manager whom I ate with, asked me for my ethnicity. Although I grew up in California, he kept trying to connect with the interests of his neighbor, who happened to be of the same ethnicity. The questions were along the lines of "My <ethnicity> neighbor, they like to play tennis. Do you like tennis? Do you follow this tennis player from <my country of origin>?"
Why there is a E stage in MESI protocol, I said I don't know, will you please teach me that? He said, NO.
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