What conflict is possible when you have a weak memory model and another memory location containing flags that indicate the status of another memory location (described above)
Design Verification Interview Questions
3,713 design verification interview questions shared by candidates
Technical questions related to digital design, based on projects from your CV and verification languages, methodologies. Questions were basic ones and there were a few scenario based questions too.
What is your expected salary?
asked in system verilog and UVM
How do you implement RAM in C++?
What is the problem of cache coherency
Second interview question: Given the following assembly commands: MOV Ri <-- Rj/immediate (put register j or immediate value into reg i) INC Ri (++) DEC Ri (--) JNZ Ri (jump not zero) 1. Code an assembly program that calculates x*y where x and y are unsigned integers 2. What values of x and y will cause the program to fail? 3. Modify the program to deal with these values 4. What result will we get if we run the program with values from question 2 and no modification from question 3? 5. Is it possible to answer question 1 without MOV command? Prove it!
Why there is a E stage in MESI protocol, I said I don't know, will you please teach me that? He said, NO.
Describe memory BIST architecture, march algorithm, MATS test. String parsing questions to process/filter verilog code encased in ifdef/ifndef. How to set up testbench for, and maximize test coverage for scan debug verification. The engineering manager whom I ate with, asked me for my ethnicity. Although I grew up in California, he kept trying to connect with the interests of his neighbor, who happened to be of the same ethnicity. The questions were along the lines of "My <ethnicity> neighbor, they like to play tennis. Do you like tennis? Do you follow this tennis player from <my country of origin>?"
Tomasulo project
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