Have I designed digital circuits.
Digital Asic Design Engineer Interview Questions
53 digital asic design engineer interview questions shared by candidates
White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.
Technical discussion about what I did in my career so far and what I should be doing if joining them.
basic digital question, rtl coding of traffic light controller
The skype interview was too technical and to ASIC-oriented. I work for 4 years. At the end of University I could answer it, now I forgot a lot...
It was a verilog question like "you are designing 2 modules that work together to send 32-bit wide payloads over a single wire"
Was asked about basic protocols for PCIE. Basic questions on CDC. Types of violations that the CDC tools complain - eg: no_sync, combi logic before double sync, multi bit double syncing, re-convergence etc. Code async reset FF and sync reset FF. What are the dis/advantages of one over the other.
Lots of questions about pmos and nmos (how to build nand gates, inverters), etc, how a pll works, how different things affect the output, transmission lines (parasitics, series vs parallel etc), flip flops, latches, op amps (designing lots of different op amps and discussing their rules)
Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
What is aliasing, and how can you make sure you aren't reading an aliased signal of unknown frequency on an oscope?
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