How would you design a circuit to do this?
Hardware Development Engineer Interview Questions
5,137 hardware development engineer interview questions shared by candidates
Questions asked were based onn FSM design, serial to parallel converter, modulo 5 operation in Verilog, clock domain crossing.
Some of the questiosn were number of clock cycles to fill a FIFO,bandwidth in cache related questions,0ne bit related problem(no of bits to cover 1/4x+3/4y expresion if both x and y are n bit)
Be careful with the behavior questions, very difficult to answer
The questions were from the topics of digital logic, ASIC design, and computer architecture.
Build a 2nand out of mux gates.
Convert a twos complement 16 bit string to compute it's absolute value.
Can you write code that resembles this pattern: 1, 1, 2, 3, 5, 8, 13, ...
Detailed questions about Voltage Supply, CAN interface safety measures and Safety measures for Lidar/Radar.
How to inverse two values in VHDL
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