Asked me in detail about phase noise in PLL
Hardware Development Engineer Interview Questions
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Some very detailed questions about pll design, and noise analysis (thermal and phase noise).
Two interviews by two people, 45 minutes. They asked timing constraints, logic simplification and analog project. They asked me to draw 2-input NAND gate and size the gate. If upper input stays high, lower input jumps from 0 to 1, compared with the other situation, which is more fast. (notice the internal node) . As for the analog project, he asks me to draw 2 stage amplifier, dc gain, first pole and second pole.
questions from fundamental RC circuits to CMOS. what is setup hold?
semiconductor memory electronics circuits digital microprocessor
How to cut clock frequency in half, questions about filtering, design using LED's and flip flops..
Talk about the projects in the resume
Design a asynchronous FIFO
opAmp, MOS, Smith Chart matching, AM,, bode plot, basic small signal analysis, stability of circuit...
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