CMOS logic for an NAND gate? Will the logic change if the input has different delays? MOSFET regions and current equation? Internal circuit of D flip flop? What is hold time and setup time?
Hardware Development Engineer Interview Questions
5,137 hardware development engineer interview questions shared by candidates
Round 1 - • Section 1 – Aptitude and Logical reasoning questions with some basic math. • Section 2 – C language based coding MCQs including pointers, arrays, and etc. and general number system questions. • Section 3 – Digital Electronics section with questions from Combinational and Sequential circuits, Boolean algebra, CMOS, BJT, ADC and DAC, etc. Round 2 - • A few questions about my resume. • Draw transfer characteristics of inverter. • What is the threshold voltage of an inverter? • What is high and low Noise margin? What does it signify • Draw CMOS inverter and mark all 4 terminals. • Draw a physical diagram of an NMOS. • What happens if the body is not shorted to source? What might happen if it is connected to a higher voltage than source? • What are state machines? • Write the Verilog code for a mod-3 counter. • What are the common mistakes one can make while writing this Verilog code? • How would you make an AND gate with a 2x1 MUX? • How would you make an OR gate with an XOR gate? Round 3 - • Asked a few general personal questions about me and resume. • A logical aptitude based question – If you have 2 cubes with 6 surfaces each, how will you any day of a month from 01 to 31 using the 2 cubes by writing any single digit number on each side of both the cube? • Implement an OR gate using NAND gates. • Draw an OR gate using a 2x1 MUX. • What is the equation of an EXOR gate? • Draw a NAND gate using CMOS logic. • Explain how it functions. • What is setup time and hold time? • What are the different types of Finite state machines? What is the difference? • Draw the state diagram of a sequence detector to detect - 01*0010*1 - where 1* means that 1 can be repeated any number of times and similarly 0*. • Verbally explain how you would write a Verilog code for a finite state machine. • Discussions regarding job location.
STA, PD, Ananlog CMOS questions, questions on stacking etc. Were asked in the second round.
I was asked about computer architecture
what's the frequnecy you used for your design, how did you tested your design. Explain area speed trade off situation you met in your design
1. Draw a FSM for a particular recognizing a particular sequence. 2. Computer Architecture - Caches, Coherency protocols (moesi mosi etc). Pipelining pro and cons. 3. Basic C questions - memcpy,linked list etc. 4. Timing violations and how to fix them.
Started with basic questions about capacitors, then asked about CMOS devices and circuits. Some questions were also based on analytical thinking and problem solving
Write verilog code for the 4 bit register? Develop a 3 input xor gate using 4:1 mux
Realizing FFs, blocking non blocking assignments, questions on CPU
Was asked to write code for a simple 2x1 mux in C and some other simple string related functions in C. Asked briefly about each of my projects and courses I have done related to digital design, vlsi. Asked which one is level/ edge triggered among Flip flop and latch. Asked basic formulas of RLC circuits. In the next round, it was mostly about OOPs, Pointers.
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