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Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
Write verilog code,difference between gate and latch,demonstrate difference between asynchronous and synchronous reset using waveform,what is a gitch
Know the 5 stage pipeline well
Explain each state in a mesi protocol.
Software (OOP, efficiency, data structures), Computer Architecture (cache coherency, pipelining), Logic (k maps, simplifying boolean expressions), and Verification (coverage, how to test, previous experience)
Difference bw asynchronous and synchronous circuits Propagation delay Static and dynamic delay
What is blocking and non blocking statement
What do you understand by low power design ? Can we use Verilog to design a low power system ?
What is metastability, and how would you prevent it?
Experience in writing RTL in the past Some hands on RTL writing
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