Most questions were from digital electronics and verilog
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
Design a module to return trigonometric sine value. Other question is related to the designing of the State Machine with the specified requirements.
FSM for a Hybrid Branch Predictor to choose between two BP using Global and Local Branch History. Design a Simple ROB and Retirement logic. Questions and Simple design on Issue Queue and Reservation station
Some basic background personal information just to get to know you.
Cache coherency, reorder buffer, memory hierarchy, register renaming, data hazards.
Mainly related to best techniques for hardware design and algorithms
Do latches have Metastability?
What is the difference between latch and flop?
Based on memories, digital design, Verilog coding
Are you willing to move to UK permanently?
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