Explain and design a two level branch predictor
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
Low power implementation - UPF Level shifters, isolation cells, retention cells, clock gating, PoR sequence etc.
I could not reveal the questions
FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
synchronization of multiple control signals FIFO Depth calculation
Design a NAND2 gate using CMOS transistors.
sync vs asyc rst
Can you sell this product? I answered that I could sell anything if I knew something about it. Supply and demand.
Questions were standard interview question on synthesis and lint
What can you offer to this company
Viewing 181 - 190 interview questions