They asked about the design verification process, UVM concepts and coverage.
Senior Design Verification Engineer Interview Questions
35 senior design verification engineer interview questions shared by candidates
Difference Between Associative array and Dynamic Arrya
Questions on UVM concepts like sequencer driver communication, monitors , scoreboards and coverage
questions about Constraints, arrays, uvm sequences etc asked.
- FIFO size requirement for write with same freq on write and read side for a burst size - A bunch of questions on polymorphism concept using parent and extended class handles and asking about the output - A bunch of questions around constraints in parent and extended class and asking what could be the values with the appropriate usage of polymorphism - A question on threads for fork join_any with delays and asking the sequence that would be seen on the output - Explain PCIe enumeration process - Explain Flow control process and the DL state machine handshake after Linkup happens
SV constraint writing UVM TB writing
There were no difficult questions.
Coding the basic skeleton code for a given design. All UVM components should be coded and explained. This includes monitors, scoreboard logic, dut, agents , sequence items, sequence , driver and test
Questions on basic debugging skills using synopsys VCS. OOP concepts. Ethernet , AXI, APB protocols and their usage. Protocol bridge
Where do you see yourself in 5 years?
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