FIFO coverage implementation in sv
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Explanation items on resume, question on PCIE behavior especially LTSSM.
Questions asked were based on the profile and the experience
The way I handle the projects from scratch and the challenges I have faced
Associative array, coverage, randomization, ahb offset address.
1. How do you login to running kubernetes pod? 2. How to start an app on kubernetes pod? 3. Architecture of kubernetes? 4. How does kubernetes work? 5. How to ssh to remote server wothout password? 6. How to generate public and private keys 7. How to copy public key to server for passwordless connection? 9. How to grep and copy to a notepad? No questions on testing, automation testing or java, selenium or python.
Full adder circuit, FIFO, Capacitance effect, C, Verilog
System verilog syntax
What will you do in case one of the projects gets a customer complaint? How will you handle it - giving feedback to the project members and making sure that the same problem never gets repeated in future?
- Constraints for Randomization of variables - Functional Coverage for the variables - Theory of SV and UVM concepts in depth -> factory, config db , - Was asked to code a driver for a given interface.
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