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Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Some question related to accessing analysis ports in a sequence ( via sequencer)
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
What is the terminal command for checking the list of active processes? What is the terminal command for checking the amount of free disk space? What does the '-x' parameter do for the `bash` command? Have you used Docker? Have you used KVM?
My previous experience, as well as a few mock examples related to verification and what my process would be
Give a detailed example of a test you wrote
Write top level test bench that sets up he virtual interface
Verification related questions.
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