Explain Cache and pipeline, how they work?
Verification Engineer Interview Questions
3,718 verification engineer interview questions shared by candidates
describe UVM Phases and difference bet run phase and main phase
Constraint and assertion , gate level simulation
Mostly on writing the code for driver monitor and scoreboard components
mostly in uvm and sv
Bit Manipulation and bit masking
I gave in 2010 for Telecom Tester.They took a written test containing questions from Reasoning and technical part.Then 2-3 round of technical containing question of Shell Scripting,SNMP (Telecom) and then a HR Round.
Write system verilog code for Monitor to monitor and check the transactions from memory.
Was given an algorithm and was asked to write a program implementing it on the board
some string manipulations in c
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