Draw diagram of jtag logic. Can you use a tdr instead of ijtag?
Verification Engineer Interview Questions
3,716 verification engineer interview questions shared by candidates
Two leetcode style questions on arrays, asked to find the output of a SV code and writing Driver class for an SPI with single master and multiple slave.
This was an entry level position. Basic questions were asked about FIFOs and metastability. Then I was asked to code an RTL Design for an Ethernet cable. Had to dissect packets of data and extract the payload while discarding everything else.
It takes 30 minutes found question like halfadder , bitwise operation , function call related problems in the verilog
What is your strengh? Tell me about yourself
Selenium commands TestNG
General interview questions, customer service experience was a focus
Q. Write assertion on a stated scenario Q. Questions on code and functional coverage
In round 1 - 19 MCQs related to general concepts, a mix of digital and analog electronics, mainly digital. 3 subjective question from - STA, STA, FIFO depth calculation 2 circuit design questions - FSM sequence generator , differently clock delayed output using MUX and flip flops. Round 2- Started with basic STA questions and went up to solving some on paper. Later digital design questions about mux , flip flop, counter, clock divider , FSM. Basic Verilog code like Fibonacci numbers generator , counter. MOS - MOS inverter questions and sub threshold region conduction. Short channel effects.
Describe the steps in an AXI transaction.
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