what factors of transistor affects the delay time
Verification Engineer Interview Questions
3,710 verification engineer interview questions shared by candidates
Basics of digital,. VLSI design etc
What is a hash table?
What is latency and throughput?
Tell me about your self do you have any projects of yours
Basics of sv, sva, verilog
My experience was bad in 2 rounds otherwise good in other 3 rounds.
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
Tell me about your previous experience.
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