MATLAB functions, DSP related questions;
Verification Engineer Interview Questions
3,710 verification engineer interview questions shared by candidates
A general question that sees how is my verification thinking. Since I had no previous experience with verification, it took my a little while to understand what was asked.
Questions about past experience with Verilog and VHDL
Strong focus on making sure Veriff and the candidate are on the same page in terms of values, future goals etc. (for example - relation to Veriff's mission)
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
It was a quetion about linked lists.
It was a quetion about pysical memroy.
detailed test plan for a synchronous fifo
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
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