What is the difference between task and function
Verification Manager Interview Questions
3,719 verification manager interview questions shared by candidates
How do you access a register and confirm it is 12 bit or not?
Can a modport include a clocking block, give an example of both.
Fota overview diagnostic flashing test and defect management procedure
Digital and SV ,UVM verilog basis
Basic sv and uvm and some digital verilog.
1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
define tlm fifo's?
Describe coverage types, describe comlexity of environmentst that you work so far, UVM reg model
given some waveforms , draw circuit
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