Computer Architecture, Logic design, validation, software, behavioral.
Verification Manager Interview Questions
3,719 verification manager interview questions shared by candidates
1. about previous experirnce
All basics of System Verilog
Not really difficult, jut really technical
What is the purpose of a capacitor and why would you want to have one or multiple on a circuit.
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
Was tested on computer architecture, pipeline, hazards, fsm, uvm basics, writing system verilog test benches for resume projects
find the minimal number of semi-binary numbers that sum up to a given number. semi-binary is an integer that is composed only by the digits 1 and 0.
about projects, verification methodologies, UVM, System Verilog testbench, Computer Arch, MESI protocol, Cache UVM testbench components, constructs Digital Design questions FSM types and differences Divided by 2 clock design and code Basic Gate level designs
Round 1: 1. What is Functional Verification? Round 2: 1. What is the difference between Verilog and System Verilog? 2. What is the difference between Blocking and Non-Blocking assignment? 3. What is an FSM 4. Mealy and Moore machine 5. What is the difference between synchronous and asynchronous design? 6. Verification using test environment 7. UVM testbench 8. Synthesis design model 9. Critical path 10. Setup time and Hold time 11. Metastable state And some more verification related stuff
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