Delay problem: A 10 ns delay is connected to one input of a NAND gate, a 2.5 ns delay inverter is connected to the other. Input is high until 10 ns, then goes high again at 50 ns. What is the behavior of the output?
Yield Manager Interview Questions
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1.Typical Phone interview with 2 Managers who asked about DRAM, NAND basic understanding, did stress on behavioral questions and stressed upon 1 question regarding difficult customer and how will you react to such situation? 2. 2nd Phone interview was taken by Area manager with rapid fire question round with basic material science, which was quiet interesting and tests your basics. 3.Onsite interview consisted of different technical rounds: interestingly the interviewers showed different SEM images and asked to find the defect. 4.Few engineers asked about semiconductor process knowledge as well as CMOS, transistor knowledge.
CMOS Basics Operation and some MOSFET related.
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Previous work experience towards the job.
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In a Silicon substrate if you dope with Boron or Phosphorus how the doping profile will behave
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