1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
nothing in particular
round robin algorithm, scheduling? state diagram?
Black box CRC circuit checking...
FIFO synchronized and asynchronized
How does Cadence Encounter solve setup time violations before CTS
ASIC flow, setup/hold, fix violation
clock divider / mealy vs moor fsm / through my resume project / setup time hold time
Explain the last project
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
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