AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
State Machine. How to verify a piece of logic.
There weren't any very difficult or unexpected questions.
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Design an arbiter. This was detailed and went on for the whole 45+ mins.
Some computer architecture questions like pipeline design and pipeline hazards
Python question and verilog question to implement the same thing
introduce your last position/ project?
basic questions about C, FSM, linux
It consisted of 2 rounds. In Round 1 they asked about basics of digital electronics, cro, osciloscope. In Round 2, they asked to code traffic light controller o verilog and discuss its area, power
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