Moderate, no unexpected questions asked.
Asic Engineer Interview Questions
1,315 asic engineer interview questions shared by candidates
What will gm change if we enlarge the W/L of a transistor by 2. Compare the gm of a BJT and MOS device. Slew rate problem
write a verilog code of moving average
min and max timing violation
You are given 2 receiver antennae and one transmitter antenna. Describe what happens to the received signal when changing the distance between receivers (close and far apart).
Write the verilog of ROB on a paper.
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
What is multicycle path, what is CDC?
They concentrate more on your technical knowledge over Architectural Design and Problems you tackle. As well as a Ciding for Automation
One hot encoding, FSM divide by 3, Verilog coding.
Viewing 1251 - 1260 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Vlsi Design EngineerVlsi EngineerAsic Physical Design EngineerSenior Asic Design EngineerSoc Design EngineerRtl Design EngineerHardware Asic Design EngineerPhysical Design EngineerSenior Dft-ingenieurHardware Engineering ManagerHardware Asic Ontwerp IngenieurSenior Fpga Design EngineerFpga Design EngineerFpga Development EngineerSenior Hardware Design EngineerSenior Asic Fpga Design EngineerAsic Design Verification Engineer