How to turn a 40% duty cycle clock signal to a half frequency signal with 50% duty cycle.
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
SRAM Design and follow up questions
how would you code an adder in verilog
Asked about the OA (1st round), like explain your answers..
What is your expected salary?
What did you do in the past, how to implement low power design, how to build CTS, how to do STA
Design FSM for sequence detector
Resume based questions
Nothing really, some pros/cons of different physical verification tools, how to filter through 100k+ errors, how to solve chip level LVS issues. Should be easy for experience engineers to answer.
what I did?
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