Project on resume, CDC questions
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Why do you want to join Synopsys?
Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
In the screening call: quetions about your background and personal projects, then 2/3 questions on digital design basics. Questions about Verilog HDL, logic synthesis, timing constraints, metastability, finite state machines, basics of verifications, testbenches, logic gates at transistor level, application of De Morgan law, small problem on digital circuits (counters, clock dividers, FSMs).
Clock Domain Crossing , RTL Design Constructs using Verilog , System Verilog and VHDL , Constraints in SDC, SDGC for spyglass
Pros and cons of vernier TDC
Digital questions, UVM environment based questions
Describe AXI bus protocol and experience with it
Can't remember.
coding questions consists of - creating sequences - creating constraints for a given problem - creating an algo for data query
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