How do design async logic?
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Do you know verilog?
1 question/quiz math related, 1 verilog code what it does and questions, 1 block diagram design and improvements, extensive talking through the behavioural part of the aptitude test with the hr manager, some sort of profiling.
design a statemachine to detect the pattern "101" in a 1-bit input stream.
about all the flow from beginning to end
Questions asked were based on the profile and the experience
Describe the process of designing for a specific FPGA. (General and very vague question prompting the interviewee to ask a lot of questions.)
Good VLSI Questions in the Interview
Once written test qualified , they called for interview In the interview process, they were asking me to solve 10 verilog programming questions, 10 puzzles In technical interview questions are design of Mux, clock generations, 2s complement design , swapping of two numbers using blocking and non blocking , parity checker design. one questions is , given the RTL code for that design the net-list circuit
what are the impacts of using very tight skew constraints
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