How to design an 64 bit adder if only given a 32 bit adder. After you design it, you will be asked how to verify it. The verification maybe related to SystemVerilog.
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
how to avoid overflow in FIFO design; design a FSM for bit string detect
VLSI, Device Physics, Cadence, Verilog and C Programming.
State machine, gate level design
Synchronous ans Asycnchronous FIFO design and verification.
Write the code of a synchronous FIFO,
The difference between blocking and non-blocking statements
Going over the resume in detail
Introduce your education background
Very theoretical questions about FF level design.
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