Compare and contrast write-through and write-back caches.
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Calculate the number of tag bits for an 8-way set associative cache with 32-bit virtual addresses that is 16kB.
How to write an assertion in SystemVerilog
What is a hardstuck bug you have encountered during a project?
Software Engineering: - Private, Protected, Public, Friend in C++ - Virtual Members, Abstract Classes, Polymorphism and Performance Impact in C++ - L-Values and R-Values, & vs && references in C++ - Atomic Operations, cache coherence protocols - Memory allocation: Heap vs stack, fragmentation, performance - Compiler optimization: Loop unrolling, tail recursion
Hardware Engineering: - Pipelining (Flushing) - Super scalar - Out of Order - Hazards (Structural) - Exceptions (Precise and Imprecise) - Branch Prediction - Speculative Execution - Tightly Coupled Memory (TCM) - Caches, Memory Hierarchy
About memory hierarchy system
Is it possible to know the taken target in case of a branch Prediction?
In case of branch Prediction is it ? possible to get 100% accuracy?
Case in verilog
Viewing 191 - 200 interview questions