Some verification related questions were asked?
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
out-of-order execution questions
For the first screening round, all questions were based on out-of-order execution CPU. For the final interview, In 1st round, I was asked questions on out-of-order execution CPU 2nd round on cache and virtual memory 3rd round had one coding question based on queues and cache-related questions
Setup and hold time constraints for latches, flip-flops as well as negative edge FF's.
What is your favorite smart phone feature?
Interrupts, virtual memory, prefetch
Introduce yourself 5 pipeline stages, the type of hazard. how to solve structural hazard, insert NO. of bubbles to solve the data hazard linked list and pointer basic knowledge.What's your plan in 10 years.
Lets talk about the 5 stage pipeline CPU you simulated in school. Walk me through what different kinds of structures are needed. And this kept on going from Instruction Fetch till Instruction Commit.
Explain the max delay and min delay violations for timing paths in a circuit?
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