The hour-long interview was mostly about the current projects.
Design Verification Engineer Interview Questions
3,712 design verification engineer interview questions shared by candidates
FSM to detect sequence
asked about uvm and system verilog.few questions about sv constraints
Generate a clock divider using or gate
Technical questions: the same as LeetCode questions - Merge Sorted Array
Traversal of a binary tree to find given value
write a system verilog code to merge two sorted array and create a merged sorted array
Mainly riddles, about gates and other components
Microprocessors, flipflops.
Questions were on digital design, FSM, waveform analysis, verilog coding with inter and intra delays, SVA, test bench scenario writing, CPU vs GPU and pipelining.
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