Delay the bus signal with BRAM.
Fpga Development Engineer Interview Questions
681 fpga development engineer interview questions shared by candidates
Where can you meet and how can you solve the hold time violation?
1) Single ended vs differential? 2) What protocols have you worked? 3) Give a block/communication scenario and asked how would you design it?
Basic questions on Analog and Digital
HR: What do you know about Maxeler? What do you think about working in a small company? Tech: Detail the FPGA structure. Explain the difference between polymorphism and function overload. If you have to build a compiler, what language would you use? Other questions about computer arithmetic.
Fourier transform
basic questions about FPGA
implement a box that have an input data (1 bit) that has pulses of 1 clock width (clk_in) and one output data that has a different clock rate (clk_out: faster/smaller), and the data should go out for only one clock pulse (in clk_out). what are the limitations in rate of such box. note that you can use only FPGA existing components
A question on FIFO depth and Constrained Random Verification
Embedded C related questions
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