FPGA designers that use Verilog are typically not good at using object oriented languages like System Verilog.
Fpga Verification Engineer Interview Questions
35 fpga verification engineer interview questions shared by candidates
What are the ways to synchronize signals and busses?
Are you open to relocation
How does AHB bus start its transaction?
Interview process. 1. Tell me about your self 2. What is your favourite subject in UG and PG. I said C programming and uP. 3. Few questions about structure and pointers, linked list 4. asked to write factorial program using recursive function. - didnt do well 5. Asked me to write a c program or pseduo code for the series 1, 22, 333, 4444, ...... etc, if i give the input is 10 it need to print the abovee series upto 10.. i didnt do well.. 6. a question about memory interfacing in uP - i didnt anwers and felt bad why i mentioned uP is my favourite subject. i have shortlisted many companies, the QP and interview process is more on technical (UG subject) finally i am not selected. From VLSI stream 3 members got slected, the pakage is 4.2L, In interview, they asked about Digital Electronics (full of sequential design ), uP and Verilog. if you are good at the UG subject you can crack the interview.
Questions about SystemVerilog, OOP concepts.
What would your past team members say your strengths/weakness are?
Tell me about yourself.
explain about ur projects??
Mostly first round HR round will be having behavioral questions.
Viewing 1 - 10 interview questions
See Interview Questions for Similar Jobs
Asic Verification EngineerFpga EngineerCpu Verification EngineerFpga Hardware Design EngineerDesign VerificationVerificationSenior Verification EngineerDesign Verification EngineerFpga Design EngineerAsic Design Verification EngineerCpu Verificatie EngineerVerification EngineerSenior Asic Verification EngineerVerification ManagerVlsi Design EngineerDigital Verification EngineerSenior Vlsi Design EngineerVerificatie Design Engineer