What is asynchronous reset.? protocols like SPI, I2C, UART. Verilog questions, FSM.
Senior Fpga Engineer Interview Questions
25 senior fpga engineer interview questions shared by candidates
How do you handle clock domain crossings for counters.
Using the whiteboard, show us how you would architect an FPGA to handle a proposed problem. Using the whiteboard, show us VHDL or Verilog code to implement an FSM.
Technical questions: - Asked to code live in VHDL (screen-sharing). - General or semi in-depth discussion about DSP knowledge or how I would implement some DSP algorithms in VHDL.
there two persons in your room . .One person is a liar and other one always says truth. but one of them possess gold with him .You are supposed to ask question to one of them and identify whether which person is possessing gold with him. What will you ask?
Logic circuits and I2C interface
Bester IP-Core in letzter Zeit?Funktionsweise, Probleme Herangehensweise.
I declined moving forward with the interview after a certain point
Asked me just about counters, ripple, etc.
A RTL coding question on how to model a signal going from one clock domain to a slower clock domain.
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