1. Explain Channel length modulation 2. Explain body effect 3. Non idealities of MOS capacitance
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Verify the Round Robin arbiter with priorities. Find nth maximum number in an array They gave various designs and asked me how would you verify it. Write the code for the scoreboard. What kind of challenges you will face while verifying the design? What is polymorphism in SV? Where do you use it? 2 x 2 router verification. In-order and out-of-order. They asked me to write the constraints for some cases for eg write followed by read on the same address. It looks like a important part of their interview process.
Why do you want to work at NVIDIA?
Design an arbiter. This was detailed and went on for the whole 45+ mins.
There were no difficult questions.
Verification questions about practical examples and real time projects scenarios
fibonacci series, OOP concepts, heap vs. stack storage, virtual class and functions
Difference between m sequencer and p sequencer in uvm?
Coding the basic skeleton code for a given design. All UVM components should be coded and explained. This includes monitors, scoreboard logic, dut, agents , sequence items, sequence , driver and test
Questions on basic debugging skills using synopsys VCS. OOP concepts. Ethernet , AXI, APB protocols and their usage. Protocol bridge
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