What is DCM and PLL?
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
sv uvm questions , sequencer grab , uvm topology etc
uvm and sv questions , sequencer grab etc
FIFO sizes and uses. Design question on clock-domain-crossing and clock synchronizers
questions about Constraints, arrays, uvm sequences etc asked.
How do you manage conflict within the team.
- FIFO size requirement for write with same freq on write and read side for a burst size - A bunch of questions on polymorphism concept using parent and extended class handles and asking about the output - A bunch of questions around constraints in parent and extended class and asking what could be the values with the appropriate usage of polymorphism - A question on threads for fork join_any with delays and asking the sequence that would be seen on the output - Explain PCIe enumeration process - Explain Flow control process and the DL state machine handshake after Linkup happens
1. they ask question related to SV, UVM and assertions coding. constraint code.
behavioral questions , Test plan for Lane change application
SV constraint writing UVM TB writing
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