Client Interview is main and is as per experience.
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Using constrained randomization what types of functional coverage would you expect to see on a PCIe bus?
Imagine you and HR manager meet in the elevator. What would you say (within 1 min) to convince him/her to hire you?
Standard coding test followed by a separate technical interview based around figuring out the root cause and solution to a real-life issue.
Constraint writing Assertion writing on given waveform
Mostly SV and methodology based and also previous projects.
There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like always @(posedge clk, reset_active) begin if(reset_active) do somthing else do something end vs: always @(posedge clk, reset_active) begin if(!reset_active) do something else do something end What is the difference in above two impl's.
Unexpected question was string manipulation using C++. Since I have not used C++ for strings since I have started working and it is not a hands-on question that has anything to do with the technical expertise of the person, it was kind of unexpected.
UVM Analysis ports and uvm testbench
About uvm Sv Ethernet Pcie Amba
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