Not too complicated
Verification Design Engineer Interview Questions
3,719 verification design engineer interview questions shared by candidates
Questions related to find a bug in the execution of a little code using nemonics, HDL structure for a state machine and HDL related questions, and OOP related questions and identifying examples in code
How do you handle multitasking?
- How yours skills will fit the position? - A behavioral question about how would you behave if you have opposite opinions with your manager
what is a good requirement?
Pipelining, FSM pattern generator, Digital logic (simple)
TDM (time division multiplexing) working and its corner cases .. FIFO questions
FSM, timing issue, perl
Virtual memory management
It was a group dealing with timing, so basically some tools related to timing analysis.
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