Verification Design Engineer Interview Questions

3,721 verification design engineer interview questions shared by candidates

What's a class, object? What does the .this operator? What are the types of FSM? What is the Grey code? Which are the components of a microcontroller? What's an interrupt? Which are the differences between RAM and ROM memories?
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Digital Verification Intern

Interviewed at Infineon Technologies

4.1
Apr 22, 2021

What's a class, object? What does the .this operator? What are the types of FSM? What is the Grey code? Which are the components of a microcontroller? What's an interrupt? Which are the differences between RAM and ROM memories?

1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
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Senior Verification Engineer

Interviewed at Infineon Technologies

4.1
Jul 22, 2023

1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors

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