Basic UVM questions, advanced systemverilog
Verification Design Engineer Interview Questions
3,721 verification design engineer interview questions shared by candidates
2.fsm design for counters
5.structre of a processor, pipelining, and cache coherence based questions
Lcm, Swap, Factorial for C coding Write constraints in system verilog
What is an asynchronous FIFO and why do we need (n+1) bit pointers.
Pipeline, risc-v, stalls, forwarding unit, hazard detection unit.
That's all i can share . Practice your basics. All the best !
Decode a CMOS transistor diagram (complex)
Some basic questions/tasks about C programming (pointers, arrays..), design task for receiving data bytes from the transmitter (C programming), Asked to explain different parts of some old SOC configuration. For people studying only Electronics I would suggest going through Software Engineering lectures from other courses to know about how memory is managed in a SOC and CPU. Ideally read about the Architecture of CPU and Microcontrollers as I was asked this in all 3 Interviews with ARM. I only studied Electronics and had no courses related to this except when we briefly looked into simple microcontrollers without going into detail so it was good decision going through Software Engineering course notes before the interview.
HR interview were standard questions. Interview with manager were more technical and based on testing and previous experiences
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