Just telephone conversation but it is very bad mention in the website and doing something different. So please be aware such fraud or HR person who is not what they said in applicaitons.
Verification Design Engineer Interview Questions
3,719 verification design engineer interview questions shared by candidates
Power of 2, asynchronized and synchronized reset
1. C++, OOP 2. python: dictionary, swap values 3. Systemverilog: fork join 4. delete repeated element in an array 5. FIFO depth 6. find SA0/SA1 amoung 128 wires in minimal steps
Design an fifo using the language of your choice and describe your thought process
Given an array of N elements and an array of M elements, both sorted in ascending order, create an array C that combines A and B in ascending order.
FSM, RISC-V questions, pipelining, hazards, cache coherency, OOP questions (Overloading, overriding, polymorphism) SV assertions to verify a rec ack protocol
Leetcode style coding problems (array and bit manipulation)
Can you talk about your past experiences?
General questions about C, pipelining, caching, hazards and more C.
design a NAND and XOR gates using MUX
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