Describe the handshake between UVM agent and UVM sequencer
Verification Design Engineer Interview Questions
3,718 verification design engineer interview questions shared by candidates
Explain gray code and FIFO techinique?
What do you do to relieve stress?
How to do numerous tasks and kill off 1 task if any finish. Then wait for all to finish.
How to deal with difficult customers
implement 4*1 mux using ternary operator
First interview was totally dedicated to the projects I had mentioned in my resume.
it was a set of basics
create a pseudo code that receives a stream of integers and calculates the sum of the highest continuous sequence on the stream : e.g. 3,5,6,-3,-12,8,-6,5,42,2,3,-4,-15,-65,24 would result in 54 ( 8-6+5+42+2+3)
C++, System verilog,uvm in c++ he asked mostly oops questions, why you want to do internship at st microelectronics, why you want to choose verification, what are your expectations will you be able to relocate
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