How did you verified for BER in a SERDES design?
Verification Design Engineer Interview Questions
3,718 verification design engineer interview questions shared by candidates
Basic verilog and design questions
About previous job role .
Questions about your experience and past jobs
Call uvm_agent function from uvm_sequence to display "hello world"
Basically they wanted to see if I can understand a large code base quickly
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
The questions were more into the current project and tool used.
Sv and UVM concepts
More on digital if you are a fresher SV , UVM would provide better opportunity
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