Verification Design Engineer Interview Questions

3,718 verification design engineer interview questions shared by candidates

Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference
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Design Verification Engineer

Interviewed at AMD

4
Mar 9, 2023

Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference

qustions asked in written test are based on the following topics 1.design of FSM 2. STA 3.design of some logic functions and reduction of logic functions face to face in interview are the questions given in the written test.
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Verification Engineer

Interviewed at Maven Silicon

2.8
Sep 12, 2016

qustions asked in written test are based on the following topics 1.design of FSM 2. STA 3.design of some logic functions and reduction of logic functions face to face in interview are the questions given in the written test.

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