Describe a difficult project you've worked on.
Verification Design Engineer Interview Questions
3,716 verification design engineer interview questions shared by candidates
The questions in the first interview were mostly about C semantics and rules. Nothing fancy, but you should know the nuances of the language.
What is your Management experience
Introduce the experience you have related to verification.
Give a situation when your input made a difference in a project.
How much of an improvement did your input make compared to the original decision? OR If there was compromises made, was the performance better or worse?
Technical questions and some logical Questions
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
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