Describe the testbench you created for a particular project
Verification Design Engineer Interview Questions
3,716 verification design engineer interview questions shared by candidates
Object overriding and overloading. Callbacks, mailboxes and semaphores
Exaplain about your project and entire data path of RISC V architecture
I do not know or care
what's something your working on to improve?
They asked me about my internship experience.
Discussed C++ Pointers. I was not expecting that topic. Also, Async Fifos, Dynamic Arrays in SV.
How do you connect UVM objects.
it was not that difficult.
Questions regarding STA mode and Transactor based Simulation Acceleration: How would you implement a transactor? Use SystemC or System Verilog and why? How will you communicate between the DUT and the transactor testbench? Explain the PCIe speedbridge interface and how would you debug it?
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