the difference of task and fuction in verilog
Verification Design Engineer Interview Questions
3,713 verification design engineer interview questions shared by candidates
Write Fibonacci function in C++
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
Computer Architecture, Logic Puzzles, SystemVerilog, C, Algorithms,Assembly
Virtual functions, forks, verification basics, OOPs principle
Find the number of '5''s in a rolling window of size 10. Flag an error when the count>4
Basic question on UVM?
What is polymorphism, how is it different from inheritance, give an example usage of polymorphism in Systemverilog testbench generation.
1. constraints 2. assertions 3. UVM topology
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
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