- Switch 2 variable's content without temporary variable. - Create an array with all the numbers from 0 to Size - 1 in random order and without duplicates.
Verification Design Engineer Interview Questions
3,713 verification design engineer interview questions shared by candidates
Draw out the circuit simple verilog code would synthesize to
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
Draw a NAND using cmos gates
How to verify a design when the frequency change?
tlm and its benefits. difference between blocking and nonblocking transactions
- about SV, FIFO design, arbiter design
MESI Protocol FIFO Verilog and condition for full and empty Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority Build a clock divider to take 2MHz signal to 1MHz Build a 4:1 MUX using behavioral verilog than structural verilog Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative) Tell me 5 stage pipeline Tell me about different hazards and explain types of data hazards how would you go beyond 5 stage pipeline
Draw a state machine that accepts the sequence 101
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