1. reverse linked list 2. calculate tree depth. 3. build a chip for sorting 4 elements by using a chip of sorting 2 elemnts.
Verification Design Engineer Interview Questions
3,718 verification design engineer interview questions shared by candidates
diference netwen testbench and design files
1. In a certain protocol why the ready signal is inout instead of out? 2. About the refresh in DDR2 3. FSM 4. System Verilog, Verilog, C, Perl, (also questions about OOP) 5. Bit operation
Program for counting the number of ones in a 32 bit number Explain FIFO Design Program to reverse all the bits of a 32 bit number
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XOR gate as Buffer and Inverter?
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questions based on logic design and vlsi
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Can u please give me 60000 I will train u and give u job
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