Q: Tell me about a time when you were NOT able to satisfy the customer and how you dealt with that?
Verification Design Engineer Interview Questions
3,719 verification design engineer interview questions shared by candidates
Q: Tell me about a time you handled a difficult customer?
What motivates me from day to day
1) Tell me about yourself.... 2) What is your best quality?
asked in system verilog and UVM
Technical questions related to digital design, based on projects from your CV and verification languages, methodologies. Questions were basic ones and there were a few scenario based questions too.
Verification plan for a given scenario, what are the possible ways we can verify.
What is the difference between calloc and malloc?
They asked: blocking, nonblocking statement, asked to write a code for a given circuit, then they asked about asynchronous, synchronous reset, how and where they are applied. In second round, they asked question based on processor design, FIFO, STA.
Phases in UVM, previous work experience and SV questions
Viewing 801 - 810 interview questions
See Interview Questions for Similar Jobs
Fpga Design EngineerVerification EngineerRtl Design EngineerVlsi Design EngineerLogic Design EngineerPhysical Design EngineerCpu Design EngineerElectrical Product Design EngineerSenior Vlsi Design EngineerSenior Fpga Design EngineerVerification ManagerSenior Asic Fpga Design EngineerApplication Design EngineerHardware Design EngineerSenior Physical Design EngineerIc Design EngineerFpga Development EngineerAsic Verification Engineer