where do you see yourself in 5 years
Asic Design Verification Engineer Interview Questions
273 asic design verification engineer interview questions shared by candidates
Tell me about a class you like?
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What's your name , is it [name] ?
I don't think the questions are difficualt. Some coding related questions I didn't answered well, mainly because my passed experiences are more focusing on the hw design, not sw coding.
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
Basics on ddr verification and functional coverage
Q: Basics of system verilog classes, creating parent class object using child class handle, $cast concept. Fork-join processes, how is control handed to code outside the fork in the 3 cases; code a watch-dog timer to time out if an event does not occur by the end of certain transaction.
Digital electronics, Perl, Verification flow
What is difference between dynamic and associative array.
Viewing 221 - 230 interview questions
See Interview Questions for Similar Jobs
Fpga Development EngineerAsic Verification EngineerHardware Asic Design EngineerFpga Design EngineerVerification EngineerVlsi EngineerDesign Verification EngineerVlsi Design EngineerFpga DeveloperSenior Asic Fpga Design EngineerFpga EngineerSenior Vlsi Design EngineerSenior Dft EngineerSenior Asic Design EngineerDesign VerificationCpu Design EngineerSenior Fpga Design EngineerDigital Asic Design Engineer